The integration of heterojunction bipolar transistors (HBTs) or bipolar junction transistors (BJTs) and field effect transistors (FETs) on a single silicon substrate is known in the art of BiCMOS. The integration of HBTs and FETs on a single chip has significantly reduced the size and cost of many electronic devices in use today. Silicon-based HBTs/BJTs and FETs, however, are known to have certain performance limitations that make them unattractive for some high-frequency analog applications, such as high efficiency cell phone amplifiers and ICs as employed in current wireless communication applications.
The fabrication of HBTs on GaAs and other III-V compound semiconductor substrates is also known and is attractive for both performance, reliability and suitability for wireless applications. Integration of HBTs and FETs would enable higher levels of integration and would provide improvements in overall integrated circuit performance. However, few practical ways of integrating both HBTs and FETs onto a single GaAs substrate are known in the art.
One previously described method involved the growth of both HBT and FET structures on a substrate by selective MBE growth. However, this approach provided inconsistent results because of epitaxial (epi) growth interruption and epi re-growth.
Another previously described method provided a combination of HBTs and FETs on a substrate by using the emitter cap layer of an HBT as a FET channel. However, the method caused an unacceptably high emitter resistance of the HBT and parasitic effects associated with the base layer that degraded FET performance.
Other efforts have included the growth of an AlGaAs/GaAs HBT on top of a High Electron Mobility Transistor (HEMT) in a single growth process. This process merged a FET into the collector of the HBT through a single epitaxial growth with only limited success because of poor performance characteristics.
A number of other attempts have been made to integrate InGaP/GaAs HBTs with MESFET and HEMT structures. In these attempts, an InGaP layer was used as the channel for the FET devices. However, the channel had low mobility and saturation velocity with high linear resistance and poor high frequency performance.
The first step in the manufacturing of such an integrated device is the production of an appropriate epitaxial wafer having the semiconductor structure from which devices can be fabricated by lithographic processes.
Accordingly, a need exists for a method of manufacture of an epitaxial wafer which would allow the suitable integration of HBT and FET devices on a single compound substrate selected from Group III-V materials.